Conversion from digital-to-analog (D/A) is the process of converting digital codes into a continuous range of analog signal levels. Digital codes are typically converted to analog voltages by assigning a voltage weight, or current weight, to each bit in the digital code and summing the voltage or current weights of the entire code. A digital-to-analog converter (DAC) having weights using the power of two is called a binary weighted DAC. DACs that produce analog current outputs usually have a faster settling time and better linearity than those that produce a voltage output.
Major factors that determine the quality of performance of DACs are resolution, sampling rate, speed, and linearity. The accuracy of the DAC's measurement and conversion is typically specified by the converter's linearity. “Integral linearity” is a measure of linearity over the entire conversion range. It is defined as the deviation from a straight line drawn between the maximum point and through zero (or the offset value) of the conversion range. “Differential linearity” is the linearity between adjacent steps of the analog output. In addition, differential linearity is a measure of the monotonicity of the converter. The converter is said to be monotonic if increasing input values result in increasing output values.
As is well known in the art, a “segmented” DAC design converts digital codes to analog signals by activating a number of weighted segments proportional to the input digital code and summing the activated segments to form the analog output signal. Current source mismatch due to process variations in current-mode digital-to-analog data converters (DAC's) results in linearity errors that reduce resolution and accuracy.
Calibration can be applied to the current sources to improve current matching and performance. In many applications employing current-mode DACs of more than 7–8 bits, some form of calibration is required, even if the DAC is segmented into MSB and LSB sub-DACs. In one calibration scheme, primary current sources of the DAC are calibrated against a single reference current source. A redundant current source is provided to replace a primary current source that is being calibrated, such that the output of the DAC does not have to be disabled to calibrate the primary current sources. The redundant current source is also calibrated during operation. As explained below, calibration is applied to one current source at a time and a calibration clock controls the sequence of calibration. The calibration operation changes from one current source to the next at the rising (or falling) edge of the calibration clock. As this process continues, each current source is periodically calibrated.
This method presents a problem since periodic calibration, which involves switching of currents, introduces a tone in the output spectrum of the DAC at the frequency of the calibration clock. This reduces DAC performance and the performance of other circuitry including these calibrated current sources. The problem can be further compounded if a segmented DAC is used. For example, when two or more current sources from different segments may be calibrated at the same time if the same calibration clock is shared between segments. This further increases the energy of the undesired tone. Furthermore, the required calibration clock and the dynamically exchanged current source elements in the array add to the cost and complexity of the DAC. Moreover, these required features add to the noise generated from the switching of current source elements for calibration and, thereby, may not be tolerable.
Thus, a need exists for a more efficient segmented current mode DAC that compensates for transistor mismatch.
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.